1. Field of the Invention
The present invention relates generally to fabrication of an array of flash memory cells for non-volatile memory devices, and more particularly, to a method and system for determining a level of misalignment of floating gate structures closest to a gate stack bending point in the array of flash memory cells.
2. Discussion of the Related Art
Referring to FIG. 1, a flash memory cell 100 of a non-volatile flash memory device includes a tunnel dielectric structure 102 typically comprised of silicon dioxide (SiO.sub.2) or nitrided oxide as known to one of ordinary skill in the art of integrated circuit fabrication. The tunnel dielectric structure 102 is disposed on a semiconductor substrate or a p-well 103. In addition, a floating gate structure 104, comprised of a conductive material such as polysilicon for example, is disposed over the tunnel dielectric structure 102. A floating dielectric structure 106, typically comprised of silicon dioxide (SiO.sub.2), is disposed over the floating gate structure 104. A control gate structure 108, comprised of a conductive material, is disposed over the floating dielectric structure 106.
A drain bit line junction 110 that is doped with a junction dopant, such as arsenic (As) or phosphorous (P) for example, is formed within an active device area of the semiconductor substrate or p-well 103 toward a left sidewall of the floating gate structure 104 in FIG. 1. A source bit line junction 114 that is doped with the junction dopant is formed within the active device area of the semiconductor substrate or p-well 106 toward a right sidewall of the floating gate structure 104 of FIG. 1.
During the program or erase operations of the flash memory cell 100 of FIG. 1, charge carriers are injected into or injected out of the floating gate structure 104. Such variation of the amount of charge carriers within the floating gate structure 104 alters the threshold voltage of the flash memory cell 100, as known to one of ordinary skill in the art of flash memory technology.
For example, when electrons are the charge carriers that are injected into the floating gate structure 104, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are injected out of the floating gate structure 104, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the flash memory cell 100, as known to one of ordinary skill in the art of electronics.
During programming of the flash memory cell 100 for example, a voltage of +9 Volts is applied on the control gate structure 108, a voltage of +5 Volts is applied on the drain bit line junction 110, and a voltage of 0 Volts is applied on the source bit line junction 114 and on the semiconductor substrate or p-well 103. With such bias, when the flash memory cell 100 is an N-channel flash memory cell, electrons are injected into the floating gate structure 104 to increase the threshold voltage of the flash memory cell 100 during programming of the flash memory cell 100.
Alternatively, during erasing of the flash memory cell 100, a voltage of -9.5 Volts is applied on the control gate structure 108, a voltage of 0 Volts is applied on the drain bit line junction 110, and a voltage of +4.5 Volts is applied on the source bit line junction 114 and on the semiconductor substrate or p-well 103 for example. With such bias, when the flash memory cell 100 is an N-channel flash memory cell, electrons are pulled out of the floating gate structure 104 to decrease the threshold voltage of the flash memory cell 100 during erasing of the flash memory cell 100. Such an erase operation is referred to as an edge erase process by one of ordinary skill in the art of non-volatile flash memory technology.
In an alternative channel erase process, a voltage of -9.5 Volts is applied on the control gate structure 108 and a voltage of +9 Volts is applied on the semiconductor substrate or p-well 103 with the drain and source bit line junctions 110 and 114 floating. With such bias during the erase operation, when the flash memory cell 100 is an N-channel flash memory cell, electrons are pulled out of the floating gate structure 104 to the substrate or p-well 103 to decrease the threshold voltage of the flash memory cell 100 during erasing of the flash memory cell 100.
FIG. 2 illustrates a circuit diagram representation of the flash memory cell 100 of FIG. 1 including a control gate terminal 150 coupled to the control gate structure 108, a drain terminal 152 coupled to the drain bit line junction 110, a source terminal 154 coupled to the source bit line junction 114, and a substrate or p-well terminal 154 coupled to the substrate or p-well 103. FIG. 3 illustrates an electrically erasable and programmable memory device 200 comprised of an array of flash memory cells, as known to one of ordinary skill in the art of flash memory technology. Referring to FIG. 3, the array of flash memory cells 200 includes rows and columns of flash memory cells with each flash memory cell having similar structure to the flash memory cell 100 of FIGS. 1 and 2. The array of flash memory cells 200 of FIG. 3 is illustrated with 2 columns and 2 rows of flash memory cells for simplicity and clarity of illustration. However, a typical array of flash memory cells comprising an electrically erasable and programmable memory device has more numerous rows and columns of flash memory cells such as 512 rows and 512 columns of flash memory cells for example.
In any case, further referring to FIG. 3, in the array of flash memory cells 200 comprising an electrically erasable and programmable memory device, the control gate terminals of all flash memory cells in a row of the array are coupled together to form a respective word line for that row. In FIG. 3, the control gate terminals of all flash memory cells in the first row are coupled together to form a first word line 202, and the control gate terminals of all flash memory cells in the second row are coupled together to form a second word line 204.
In addition, the drain terminals of all flash memory cells in a column are coupled together to form a respective bit line for that column. In FIG. 3, the drain terminals of all flash memory cells in the first column are coupled together to form a first bit line 206, and the drain terminals of all flash memory cells in the second column are coupled together to form a second bit line 208. Further referring to FIG. 3, the source terminal of all flash memory cells of the array 200 are coupled together to a source voltage V.sub.SS, and the substrate or p-well terminal of all flash memory cells of the array 200 are coupled together to a substrate voltage V.sub.SUB.
FIG. 4 illustrates the lay-out for forming the array of flash memory cells 200. In FIG. 4, the control gate structure for a row of flash memory cells is continuous including a first control gate structure 212 for the first row of flash memory cells and a second control gate structure 214 for the second row of flash memory cells. Each flash memory cell within a row is defined by a floating gate structure patterned below the control gate structure of that row. For example, the first row of flash memory cells of FIG. 4 includes a first floating gate structure 216, a second floating gate structure 218, a third floating gate structure 220, and a fourth floating gate structure 222.
FIG. 5 shows the cross-sectional view of the gate stack formed under the first control gate structure 212 across dashed line A--A in FIG. 4. Such a gate stack includes a tunnel dielectric structure 224 similar to the tunnel dielectric structure 102 of FIG. 1, and includes a floating dielectric structure 226 similar to the floating dielectric structure 106 of FIG. 1. The floating dielectric structure 226 is disposed between the control gate structure 212 and the floating gate structures 218 and 220. The floating gate structures 216, 218, 220, and 222 are electrically isolated from each other by a layer of insulating material 228.
Each of the control gate structures in FIG. 4 including the first and second control gate structures 212 and 214 have a plurality of floating gate structures defined within the gate stack formed under a control gate structure. Each of the floating gate structures defines a respective flash memory cell. The drain bit line junction and the source bit line junction of a flash memory cell are formed within the semiconductor substrate adjacent the respective floating gate structure corresponding to the flash memory cell.
FIG. 6 shows the cross-sectional view of the flash memory cells formed by a fifth floating gate structure 230 under a third control gate structure 232 and by a sixth floating gate structure 234 under a fourth control gate structure 236, across dashed line B--B in FIG. 4. The flash memory cells of FIG. 6 include tunnel dielectric structures 238 and 240 that are similar to the tunnel dielectric structure 102 of FIG. 1, and include floating dielectric structures 242 and 244 that are similar to the floating dielectric structure 106 of FIG. 1.
Further referring to FIG. 6, a source bit line junction 246 is formed with the portion of the semiconductor substrate or p-well 103 disposed between the gate stacks formed by the third and fourth control gate structures 232 and 236. A drain bit line junction 248 for the fifth floating gate structure 230 is formed with the portion of the semiconductor substrate or p-well 103 disposed to the north of the third control gate structure 232 in FIG. 4. Similarly, a drain bit line junction 250 for the sixth floating gate structure 234 is formed with the portion of the semiconductor substrate or p-well 103 disposed to the south of the fourth control gate structure 236 in FIG. 4.
Referring to FIGS. 4 and 6, the source bit line junction for each of the floating gate structures disposed under the first and second control gate structures 212 and 214 is formed by the same portion of the semiconductor substrate or p-well 103 disposed between the first and second control gate structures 212 and 214. On the other hand, the drain bit line junction for a pair of floating gate structures disposed under the second and third control gate structures 214 and 234 and vertically aligned in a same column are formed by the same portion of the semiconductor substrate or p-well 103 disposed between the second and third control gate structures 214 and 232. An example drain contact structure 252 in FIG. 4 is disposed over such a drain bit line junction formed with the portion of the semiconductor substrate or p-well 103 disposed between the second and third control gate structures 214 and 232. Such a pattern of the drain and source bit line junctions repeats for each adjacent pair of control gate structures.
Each of the drain bit line junctions formed for a row of flash memory cells within the portion of the semiconductor substrate or p-well disposed between control gate structures are electrically isolated from each other by shallow trench isolation structures (not shown in FIG. 4 for clarity of illustration). The drain contact structures in FIG. 4 that are vertically aligned in a column are electrically coupled to form a bit line of the array of flash memory cells, whereas each control gate structure forms a word line of the array of flash memory cells.
In addition, the source bit line junction for each of the floating gate structures disposed under a pair of adjacent control gate structures is formed by the portion of the semiconductor substrate or p-well disposed between the pair of control gate structures. Source contact structures are periodically formed on the semiconductor substrate or p-well disposed between the pair of control gate structures to provide connection to the source bit line junction. Examples of such source contact structures include a first source contact structure 254 and a second source contact structure 256 formed periodically with four flash memory cells between each adjacent pair of source contact structures in FIG. 4.
Typically, more numerous flash memory cells are disposed between two adjacent source contact structures, but four flash memory cells are illustrated between two adjacent source contact structures for simplicity and clarity of illustration. In addition, FIG. 4 shows a portion of an array of flash memory cells for a flash memory device for simplicity and clarity of illustration. The pattern of flash memory cells of FIG. 4 repeats with more numerous control gate structures and floating gate structures for a larger array of flash memory cells for a typical non-volatile flash memory device.
Referring back to FIG. 4, a control gate structure bends to surround the larger area occupied by a source contact structure. For compact lay-out of the array of flash memory cells, the flash memory cells are formed to be relatively near each other. However, a contact structure typically requires a larger area than a flash memory cell. Thus, the control gate structures bend to surround the larger area occupied by source contact structures in FIG. 4.
Referring to FIGS. 4 and 7, FIG. 7 shows an enlarged view of the first source contact structure 254 with bending of the gate stacks formed by the first and second control gate structures 212 and 214. The first floating gate structure 216 is formed to the right of the source contact structure 254 under the first control gate structure 212, and a seventh floating gate structure 260 is formed to the left of the source contact structure 254 under the first control gate structure 212. An eight floating gate structure 262 is formed to the right of the source contact structure 254 under the second control gate structure 214, and a ninth floating gate structure 264 is formed to the left of the source contact structure 254 under the second control gate structure 214.
When the floating gate structures in the array of flash memory cells are properly aligned, the first, seventh, eighth, and ninth floating gate structures 212, 260, 262, and 264 are disposed at a displacement distance 266 away from a gate stack bending point when the control gate structures 212 and 214 begin to bend. Each of the floating gate structures 212, 260, 262, and 264 are patterned to have a substantially same desired area. When the floating gate structures in the array of flash memory cells are properly aligned as illustrated in FIG. 7, each of the floating gate structures 212, 260, 262, and 264 have a substantially same desired area.
On the other hand, referring to FIGS. 8 and 9, when the floating gate structures in the array of flash memory cells are not properly aligned, the areas of the floating gate structures are patterned into the bended portions of the control gate structures 212 and 214. In FIG. 8, the floating gate structures 216, 260, 262, and 264 are misaligned by being shifted too much to the left direction by a misalignment level of distance 268. In that case, the areas of floating gate structures 216 and 262 adjacent to the right of the source contact structure 254 occupy the bended portion of the control gate structures 212 and 214 to result in a larger area of each of the floating gate structures 216 and 262. On the other hand, in FIG. 9, the floating gate structures 216, 260, 262, and 264 are misaligned by being shifted too much to the right direction by a misalignment level of distance 270. In that case, the areas of floating gate structures 260 and 264 adjacent to the left of the source contact structure 254 occupy the bended portion of the control gate structures 212 and 214 to result in a larger area of each of the floating gate structures 260 and 264.
During an erase operation of the flash memory cells of the array of flash memory cells, charge carriers such as electrons are pulled out of the respective floating gate structure of each flash memory cell to decrease the threshold voltage of each flash memory cell. Typically, same bias voltages are applied at terminals of each of the flash memory cells of the array during this erase operation. A higher amount of charge carriers are pulled out of the floating gate structure of a flash memory cell when the area of the floating gate structure is larger to result in a lower threshold voltage when the charge carriers are electrons. However, a lower threshold voltage results in higher undesired leakage current of the flash memory cell, as known to one of ordinary skill in the art of non-volatile flash memory devices. Thus, referring to FIGS. 8 and 9, misalignment of the floating gate structures into the bended portion of the control gate structures with increase in area of the floating gate structures is undesired because of the increase in the leakage current for the flash memory cells formed by such floating gate structures.
Thus, a mechanism is desired for determining the level of misalignment of floating gate structures in an array of flash memory cells.